1. Field of the Invention
This invention relates to a system of identifying an individual chip by laser scribing unique identification codes on that chip and the use of those codes during and after fabrication of a semiconductor device.
2. Prior Art
The fabrication of electrical components and in particular, integrated circuits, typically employs fabrication techniques wherein slices or wafers of a semiconductive material, such as silicon, are processed to contain a large number of devices. That is, each wafer or slice contains a number of individual circuits. The wafers are configured to have areas facilitating dicing of the wafer into discrete integrated circuit chips. Batch processing techniques are conventionally used in the fabrication of such semiconductor wafers and dicing into integrated circuit chips. Following batch processing, the individual chips are then tested, sorted, and eventually placed on integrated circuit modules.
In handling chips on an individual basis, errors in sorting may occur, chips may be mis-oriented when placed on the modules or, a chip of the wrong configuration is utilized. Thus, there is a need to identify each chip with a unique code such that its history can be accurately tracked from initial sorting established during testing, through dicing and through failure detection during system test and field returns of a commercially used device. Such an identification number should preferably be both machine and human readable and accurately describe, or lead to routinely generated production control information describing not only the chip part number identification but other supplementary manufacturing data such as manufacturing line, date of manufacture, unique conditions of manufacture and the like. This identification number would then be used in subsequent manufacturing steps. It would be employed to verify chip placement in a chip storage bank, to verify chip placement on a multi-chip substrate prior to reflow joining of that chip to the substrate and finally, to determine the individual chip identification for subsequent failure analysis. No electrical interaction is made with the chip to write or read the identification, such interaction being self-defeating to this system.
Within the prior art, no system is available to perform these tasks. U.S. Pat. No. 4,150,331 discloses an individual chip identification utilizing programmable circuitry on the chip surface in which a signature for that chip may be encoded. In accordance with this patent, diodes or other unidirectional current-conducting devices are connected between selected I/O pins in a common bus which is connected to a test and diagnostic pin. A digital identification number is used by the placement of diodes such that the composite circuitry defines a chip signature in binary form.
Such a technique, while providing identification for an individual chip, is not human readable and requires specific I/O circuitry to determine the identification of a particular chip. Additionally, the technique uses valuable chip area that would otherwise be employed for fabrication of a device. Additionally, if comprehensive data is to be placed on the chip, an excessive number of logic devices are required. Additionally, electrical activity within the chip to interrogate the identification may be in error, resulting in a false identification.
U.S. Pat. No. 4,027,246 relates to an automated integrated circuit manufacturing system wherein each wafer physically carries an identification code. The system describes a technique for reading the identification for each of the wafers and then transporting the wafers in accordance with their identity from a random access wafer storage unit to subsequent processing steps. The system operates under computer control such that wafers are received from the random access storage station may be read and based on the identification of the wafer, selectively gated for fabrication into large scale integrated circuit devices. The system operates for purposes of identification at the wafer level and therefore once those components are diced, no affirmative identification of individual chips is made.
The following patents and publications are representative of other art dealing with techniques of product identification.
U.S. Pat. No. 3,558,899 entitled "System and Method for Using Numerically Coded Etched Indicator Identification of Pieces of Semiconductor Material", issued Jan. 26, 1971;
U.S. Pat. No. 3,562,536 entitled "Radiation Sensitive Semiconductor Wafter Identification System", issued Feb. 9, 1971;
U.S. Pat. No. 3,597,045 entitled "Automatic Wafer Identification System and Method", issued Aug. 3, 1971;
U.S. Pat. No. 4,010,355 entitled "Semiconductor Wafer Having Machine Readable Indicies", issued Mar. 1, 1977;
U.S. Pat. No. 4,047,000 entitled "Control System for Computer Controlled Identification of Bottles", issued Sept. 6, 1977;
U.S. Pat. No. 4,201,338 entitled "Mold Identification, issued May 6, 1980;
IBM Technical Disclosure Bulletin, R. R. Jorgensen, Vol. 14, No. 4, Sept. 1971, pp. 1023-1025;
IBM Technical Disclosure Bulletin, "Chip Sorting", J. P. Wilson, Vol. 14, No. 5, Oct. 1971, p. 1479; and
IBM Technical Disclosure Bulletin, "Identification of Wafers by Marginal Binary Notching and Template", J. S. Jackson, et al, Vol. 15, No. 7, Dec. 1972, pp. 2273-2274.